1. Field of the Invention
This invention relates to computer systems, and more particularly, to a new power bus grid structure to be used in the layout of circuits on semiconductor substrates.
2. History of the Prior Art
When semiconductor circuits such as complementary metal-oxide semiconductor (CMOS) circuits are manufactured, the individual devices are laid out on a substrate in essentially rectangular groups of cells. The individual cells of each group are designed to accomplish one particular function in the overall operation of the circuit such as to provide an AND logic function. Each group of cells, on the other hand, is typically designed to accomplish some larger sub-function of the entire circuit on the substrate; for example, one group might function as an address decoder.
The rectangular nature of the groups is determined by the need to conserve die space and to provide power to the devices of the cells through a pair of power buses carrying the voltages generally referred to as Vcc and Vss. In order to place the largest number of cells on a substrate, the two power buses are typically arranged in parallel across the portion of the substrate occupied by the group; and a number of cells are placed side by side and connected to the parallel buses to receive power. These power buses are typically provided by the first metal layer (metal 1) applied to the substrate in producing the devices of the cells. The pattern of parallel buses with connected cells forming a row is repeated by a plurality of similar pairs of metal 1 power buses in additional rows lying parallel to the first row sufficient to provide power to all of the cells of the group. Constraining these cells to fit within the structure provided by the parallel pairs of buses causes the overall pattern of most groups to be rectangular.
In addition to the metal 1 power buses which define the parallel rows for powering the individual cells, some means must be provided for furnishing power to these metal 1 power buses from the upper layers of the semiconductor. Furthermore, the individual cells of the group require interconnections between one another to carry out the functions of the group, connections must be made to other circuitry on the substrate which mounts the entire circuit, and the individual devices in each cell must be appropriately interconnected. These interconnections are typically accomplished by conductors of the metal 1 layer. The interconnections to provide power to the power buses of the metal 1 layer of the group are typically provided by parallel metallic conductors of a second metal layer (metal 2) which form a pattern at right angles to and on top of the power conductors of the metal 1 layer described above. These metal 2 conductors connect to the power buses of the metal 1 layer. In turn, connections to the power providing conductors of the metal 2 layer are typically provided by metallic conductors of a third metal layer (metal 3) which run parallel to one another and to the power conductors of the metal 1 layer. In more advanced circuits such as those manufactured using a 0.5 micron process, a fourth layer of metal conductors (metal 4) lies parallel to the conductors of the metal 2 layer over all of the other layers of power conductors and provides connections to the main power sources. All of these metallic power conductors are variously connected to one another to provide power to all of the devices of all of the cells.
In addition to carrying power to the devices of the cells metal conductors provide, the various interconnections between the cells by which signals are transferred. As has been pointed out, most of the connections within a cell are made by conductors in the metal 1 layer. However, each of the metal 2 and metal 3 layers are also used to interconnect the cells and provide the signals appropriate to the circuit functions which the cells carry out.
As the circuitry placed on a semiconductor substrate becomes smaller in size and more complicated, it becomes more difficult to make the connections to the devices within a cell which must be connected to other cells and other circuitry. This occurs because there are more devices; the area allotted to each cell is smaller; there are more metallic signal conductors interconnecting the devices on the metal 1 layer leaving little room to access the connection nodes; and the power conductors of the metal 1, metal 2, metal 3, and metal 4 layers cover more of the area used by the devices within the cell so that nodes to which connections may be made are often covered and inaccessible.
It is desirable to provide a power busing arrangement which provides better access to nodes of the devices on a semiconductor substrate than do arrangements known to the prior art.